An output signal of a logic gate will exhibit a delay when compared to an input digital signal received by the logic gate. For example, if an input digital signal being received by a logic gate undergoes a transition, there will be a finite time period (a delay) before the transition of the input digital signal has an impact on the output signal. When modelling such gates by following the classical Muller's approach, a logic gate is regarded as an atomic evaluator of a Boolean function with a delay associated with its output. A logic gate may alternatively be referred to as a logic block.
Behaviour of an asynchronous circuit may be specified using a Signal Transition Graphs (STG). STGs are a type of Petri net in which transitions are labelled with the rising edges (denoted by a “+”) and falling edges (denoted by a “−”) of circuit signals. FIG. 1 is an STG showing a causality relation 100, a concurrency relation 102 and a conflict relation 104.
A Petri net, for example of the type shown in FIG. 1, is a directed graph with two types of nodes: places and transitions. Places are represented by circles (for example 106) and transitions are represented by textual labels (for example 108). Places can be connected to transitions by means of consuming arcs, and transitions can be connected to places by producing arcs. Producing and consuming arcs are denoted by arrows (for example 110).
The state of a Petri net is determined by its marking. Marking is characterised by the number of tokens in a specific place of the Petri net. A token is typically denoted by a dot (for example 112). The marking of a Petri net can evolve by means of a token game whose rules are as follows. A transition having all preceding places marked becomes enabled. An enabled transition may eventually fire by reducing the number of tokens in every preceding place by one and increase the number of tokens in every succeeding place by one as an atomic action. This firing leads to a new marking which defines the next state of the Petri net.
For simplicity, places with one consuming arc and one producing arc are often hidden, allowing arcs (with implicit places) directly between pairs of transitions. STGs are a convenient model for capturing causality (order of events), concurrency (interleaving of independent events) and conflict (choice of one scenario from several possibilities) relations on circuit signals, as shown in FIG. 1.
Interpretation of STGs of the type presented herein will be well understood by the skilled person.
A delay comparator is a type of circuit that may be used to compare the relative timing of events. For example, a delay comparator receiving two digital input signals exhibiting transitions at different times can be used to identify which digital input signal transitioned first.
FIG. 2 is a schematic of a capacitance to digital converter (CDC) 200 using iterative delay chain discharge and comprising a delay comparator 202 (Wanyeong Jung et. al., A 0.7 pF-to-10 nF Fully Digital Capacitance-to-Digital Converter Using Iterative Delay-Chain Discharge, ISSCC 2015/Session 27/Physical Sensors/27.6). FIG. 3 is a further schematic of the delay comparator 202. The delay comparator comprises inverters 204, 206, 208, 210, NAND gates 212, 214, 216 and an XOR gate 218. The delay comparator 202 receives the two signals V_SENSE_Delay and V_LOW_Delay at inputs of the inverters 204 and 206, respectively, and the delay comparator 202 provides an output Y at an output of the NAND gate 216. NAND gate 216 also receives a signal Output_Enable and XOR gate 218 output a signal Done. Output Y is dependent on the relative timing of the delays of V_SENSE_Delay and V_LOW_Delay.
The delay comparator 202 requires that both signals V_SENSE_Delay and V_LOW_Delay have undergone and completed their transitions for a pulse to be provided on output Y. Therefore a single transitioning signal is insufficient to provide a pulse on the output Y.
Known systems implementing capacitance and voltage conversion to digital code are presented in Delong Shang et. al., Low Power Voltage Sensing Through Capacitance to Digital Conversion, Proc. Int. Symp. on Design and Diagnostics of Electronics Circuits & Systems (DDECS), 2016; Kaiyuan Gao et. al., Fast Capacitance-to-Digital Converter with Internal Reference, Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), 2016; and Y. Xu et. al., A Smart All-Digital Charge to Digital Converter, Proc. International Conference on Electronics Circuits and Systems (ICECS), pp. 668-671, 2016. These known systems comprise components exhibiting similar functionality to the delay comparator 202.
An asynchronous arbiter, for example as shown in C. Seitz, Ideas about arbiters, Lambda pp 10-14, 1980; and D. Kinniment, Synchronization and arbitration in digital systems, Wiley Publishing, 2008 may be used to receive multiple input signals that exhibit transitions between high and low states. The asynchronous arbiter is used to select one of the input signals and to provide an output that is associated with the selected input signal. For example, if one of the input signals undergoes frequent transitions where each transition has an associated output, and the other input signal is dormant (and exhibit no transitions), then the asynchronous arbiter will provide the outputs associated with the frequently transitioning input signal every time; the dormant input signal will be ignored. However, if both input signals exhibit transitions at a similar time, then the asynchronous arbiter will decide which input signal is to be selected, and its associated output provided, first. A “fair” arbiter provides the associated output of the input signal that was not selected after the associated output of the selected input signal has been provided. The asynchronous arbiter has a different purpose and different protocol from a delay comparator. Additionally, it is not well-suited for making repeated comparisons of the relative timing of events.